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| Manishkumar Patel Test Engineer Qualcomm |
Abstract
Reducing the cost of test (COT) has been a steadfast mission for test engineers and test operations teams for a long time. In the semiconductor industry, the increasing complexity and shrinking geometries of today’s system on chip (SOC) and system in package (SIP) IC designs has driven the cost of test up as a percentage of the total product cost. The application of statistical process control-based (SPC) techniques using real-time information for truly adaptive test is a proven solution gaining rapid acceptance. This case study examines the production implementation of SPC-based real-time sampling on an analog IC from Qualcomm. A significant test time reduction was achieved. The step by step process with subsequent results is shown below.
I. Problem Statement
A wide variety of issues and challenges affect semiconductor test these days. Just a few of these are:
- Increasing gate counts
- Multiple cores on today’s SOC and SIP designs (requiring a mix of test strategies)
- Smaller fab geometries
- Increasing need for yield learning information
- Higher operating frequencies
- Increasing number of functional levels
- Wide variety of proprietary ATE solutions with little standardization
- Reaching the physical limits of parallelism capabilities
Time-to-market, time-to-volume, time-to-target-yield, and time-to-decision concerns
Common to all of these issues is one fundamental concern - the cost of test (COT). The cost of test is increasing as a factor in the over-all cost of manufacturing ICs and, as such, is an area for industry focus, innovation and improvement.
A widely accepted COT formula is the following;
COT = (Capital + Operating Costs) / (Yield * Utilization * Throughput)
The variable for this formula are as follows:
- Capital – the depreciation of capital equipment (testers, probers, handlers, and possible amortization of facilities modifications or manufacturing infrastructure)
- Operating Costs – facilities, maintenance, labor, consumables, and any additional overhead
- Yield – the production yield for a given device
- Utilization – the percentage of time used for production (excluding engineering use, maintenance use, and idle time)
- Throughput – the number of parts tested for a given unit of time
As illustrated in the figure below (using the COT formula above), throughput has a dramatic impact on the cost of test. While holding all other variables constant, the analysis shows the cost of test as it relates to UPH.
One main thrust of managing the cost of test is focus on increasing throughput by reducing the time it takes to perform test. The cost of test in today’s semiconductor environment can be as much as 40 to 50% of the materials, labor and overhead (MLO) costs for a given device. This has re-energized the industry towards finding new methods that reduce the cost of test. When boiled down to its’ simplest form, in the world of semiconductor test – it’s all about seconds and pennies and they both add up quickly.
In the outsourced test model, the cost of a test second is aggressively negotiated and in the captive test model, the cost of a test second is carefully defined, monitored, and managed. In both cases, the test time of any given device is worked diligently for optimization.
A typical product test engineering team has to report in to operations management, the business unit management, and corporate management what they are doing to improve the cost of test. There are a variety of techniques that have been employed over time to lower the test time of any given device. It is important to note that SPC-based sampling techniques are additive to these traditional test time reduction methods. The hand optimizing of test sequencing, test process optimization, implementation of multi-site testing at both wafer sort and final test, and DFT methods such as scan, IDDQ, and BIST, can all be incrementally added to with additional test time reduction via sampling.
II. Thesis Statement
Statistical process control-based (SPC) sampling techniques at semiconductor test can achieve significant cost of test improvements through test time reduction (TTR) while maintaining excellent test coverage and quality levels. Dynamic and adaptive sampling methods can achieve optimum results across a wide variety of product types and production yields with very minimum engineering effort.
III. Program Description
Management at Qualcomm recognized that they were reaching the limits of potential test time reduction using labor-intensive manual optimization techniques and also migrating to quad site testing. Having carefully chosen the fastest testers they could, they were challenged as to how to squeeze further time out of their high volume testing. To do so would mean millions of dollars of savings and faster response time in the market place. Furthermore, since Qualcomm uses third party test subcontractors extensively, they would need a solution that was easy to deploy and maintain around the world.
Having studied the potential of SPC sampling internally, Qualcomm was anxious to find a commercially supported product that was a mature and proven solution that had no undesired impact on outgoing quality levels. They also wanted a solution that provided a solid return on investment (ROI) through a significant test time reduction (TTR.) These requirements were a fundamental cornerstone of the evaluation and decision-making process that led them to Pintail Technologies -a leader in innovation in the area of real-time semiconductor test optimization.
In order to evaluate the entire process of selecting a device and implementing real-time sampling, the following steps were taken by the Qualcomm and Pintail engineering teams:
Device selection – Qualcomm chose a high volume analog IC that was in full production with steady yields and had already been optimized to the extent practical with manual methods.
Test program analysis – the analog IC chosen has a total of 400+ tests within its’ test program with a high degree of parametric test content.
Proposed sampling plan – Upon careful analysis between the Qualcomm team and Pintail team, a sampling plan was developed that involved a number of tests that were in statistical control (ISC) and contributed high portions of overall test time. Tests that are “Must Test” exceptions are identified and excluded from sampling by the product engineer.
- Device Profile creation – a Pintail Device Profile was created to govern the statistical sampling plan in real-time mode while testing. This Device Profile is extremely flexible and configurable by the user both on a global basis and on a test by test basis.
- Simulation – the Device Profile was then used in the Pintail TestVision® analysis tool to simulate the sampling results. A potential TTR of just under 20% was confirmed via the simulation as applied against the 44 ISC tests being sampled.
- QA testing to compare the quality of lots with sampling vs. lots with 100% test - the QA team at Qualcomm wanted to ensure their quality standards were being maintained. 10,000 to 30,000 devices total were tested with sampling turned on and tested again with sampling turned off.
- QA testing analysis – a variety of statistical analysis techniques were used on the two data sets (t-test, standard error, Cp, Cpk, standard deviation, etc…) to provide proof of the nonimpact to quality levels. The results from the QA comparison testing (with sampling on vs. sampling off) showed no perceptible changes in outgoing quality.
- QA buy-off – the Qualcomm QA team carefully reviewed the results of the QA testing analysis with their testing subcontractors and signed off on the release to production (RTP) of this device with sampling implemented.
- Production implementation – the SwifTest-Monitor thin client application was easily installed on the outsourced ATE platforms, the new test programs were loaded and a quick correlation run was executed in accordance with the subcon’s RTP process.
- Post RTP - Using Pintail’s SwifTest-Monitor, Qualcomm and their test subcontractors can continually monitor testing results looking for additional tests to come into statistical control and thereby becoming new candidates for test time reduction.
IV. Program Analysis & Results
The release to production occurred smoothly at the initial subcontracted test location and the TTR of 18.16% was realized.
Other points relevant to implementing Pintail Technologies’ SPC-based sampling in production:
- The technique can be used effectively at both wafer probe and final test.
- Support for single site, multi-site and dual head test systems.
- Works on multiple ATE platforms.
- The process of analyzing test for being in statistical control (ISC) leads naturally to improvements in yield and test programming efficiency. The better the yield, the better the savings become with dynamic sampling.
- Benefits to subcons include improved responsiveness to customer demands and production variations.
- Pintail’s support network includes sales and applications engineering throughout the U.S., Europe, and Asia
V. Summary and Conclusions
Pintail Technologies’ SwifTest-Monitor™ and SwifTest-MX™ software solutions were implemented in production to govern real-time statistical sampling on an analog IC from Qualcomm. The test time was reduced by over 18%; with no perceptible impact to outgoing quality levels.
The economic benefits of SPC sampling are illustrated in the graphic below: assumptions for this tops-down, gross capacity-based analysis are for a single tester, running full time at a 70% utilization and efficiency rate. The X axis is varying cost of test (per test second) in half-cent increments and the Y axis represents the dollarized annual savings with an 18.16% test time reduction used.
A savings example:
- Cost of test = $.05 using 5 testers worth of capacity (at a 70% utilization & efficiency rate). An 18.16% TTR will result in savings of just under $1M dollars per year.
References:
- ‘ITRS 2005 Report – test and test equipment section’, SEMATECH, Jan. 2006.
- Jack Horgan, ‘Test & ATE – cost of test’, EDA Weekly, March 8-12, 2004.
- Richard Kittler, ‘Challenges for use of statistical software tools in the semiconductor industry’, Yield Dynamics, Proc. Joint Statistical Meetings (JSM2000), August, 2000.
- Gregory Dionne, ‘Approaching device-limited test time’, Semiconductor Test Newsletter, Spring Issue, 2004.
- Steven E. Shultz, ‘Introduction: Design for Manufacturability’, Future Fab International, Volume 19, June, 28, 2005.
- Risto Puhakka, ‘Cost of Test: the big driver in ATE’, Future Fab International, Volume 19, June, 28, 2005.
- Randy Kramer and Dan Proskauer, ‘ATE implementations for multi-site device test’, Evaluation Engineering, July, 2005.
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